L
OW
N
OISE
, H
IGH
L
INEARITY
P
ACKAGED
PHEMTT
•
PERFORMANCE (1850 MHz)
♦
27 dBm Output Power (P
1dB
)
♦
18 dB Small-Signal Gain (SSG)
♦
1.2 dB Noise Figure
♦
42 dBm Output IP3
♦
45% Power-Added Efficiency
♦
Evaluation Boards Available
♦
Featuring Lead Free Finish Package
FPD1500DFN
•
DESCRIPTION AND APPLICATIONS
The FPD1500DFN is a packaged depletion mode AlGaAs/InGaAs pseudomorphic High Electron
Mobility Transistor (pHEMT). It utilizes a 0.25
μm
x 1500
μm
Schottky barrier Gate, defined by
high-resolution stepper-based photolithography. The recessed and offset Gate structure minimizes
parasitics to optimize performance, with an epitaxial structure designed for improved linearity over a
range of bias conditions and input power levels. The FPD1500DFN is available in die form and in
other packages.
Typical applications include drivers or output stages in PCS/Cellular base station high-intercept-
point LNAs, WLL and WLAN systems, and other types of wireless infrastructure systems.
•
ELECTRICAL SPECIFICATIONS AT 22°C
Parameter
Power at 1dB Gain Compression
Small-Signal Gain
Power-Added Efficiency
Noise Figure
Output Third-Order Intercept Point
(from 15 to 5 dB below P
1dB
)
Symbol
P
1dB
SSG
PAE
NF
IP3
Test Conditions
V
DS
= 5 V; I
DS
= 50% I
DSS
V
DS
= 5 V; I
DS
= 50% I
DSS
V
DS
= 5 V; I
DS
= 50% I
DSS
;
P
OUT
= P
1dB
V
DS
= 5 V; I
DS
= 50% I
DSS
V
DS
= 5V; I
DS
= 50% I
DSS
Matched for optimal power
Matched for best IP3
Saturated Drain-Source Current
Maximum Drain-Source Current
Transconductance
Gate-Source Leakage Current
Pinch-Off Voltage
Gate-Source Breakdown Voltage
Gate-Drain Breakdown Voltage
I
DSS
I
MAX
G
M
I
GSO
|V
P
|
|V
BDGS
|
|V
BDGD
|
V
DS
= 1.3 V; V
GS
= 0 V
V
DS
= 1.3 V; V
GS
≅
+1 V
V
DS
= 1.3 V; V
GS
= 0 V
V
GS
= -5 V
V
DS
= 1.3 V; I
DS
= 1.5 mA
I
GS
= 1.5 mA
I
GD
= 1.5 mA
0.7
12
12
375
40
42
465
750
400
1
0.9
18
18
15
1.3
550
mA
mA
mS
μA
V
V
V
dBm
Min
Typ
27
18
45
1.2
Max
Units
dBm
dB
%
dB
RF SPECIFICATIONS MEASURED AT
f
= 1850 MHz USING CW SIGNAL
Phone:
+1 408 850-5790
Fax:
+1 408 850-5766
http://www.filtronic.co.uk/semis
Revised:
11/14/05
Email:
sales@filcsi.com
L
OW
N
OISE
, H
IGH
L
INEARITY
P
ACKAGED
PHEMTT
•
ABSOLUTE MAXIMUM RATINGS
1
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain-Source Current
Gate Current
RF Input Power
2
Channel Operating Temperature
Storage Temperature
Total Power Dissipation
Gain Compression
Symbol
V
DS
V
GS
I
DS
I
G
P
IN
T
CH
T
STG
P
TOT
Comp.
Test Conditions
-3V < V
GS
< +0V
0V < V
DS
< +8V
For V
DS
> 2V
Forward or reverse current
Under any acceptable bias state
Under any acceptable bias state
Non-Operating Storage
See De-Rating Note below
Under any bias conditions
-40
Min
Max
8
-3
I
DSS
15
350
175
150
2.2
5
Units
V
V
mA
mA
mW
ºC
ºC
W
dB
%
FPD1500DFN
Simultaneous Combination of Limits
3
2 or more Max. Limits
80
1
2
T
Ambient
= 22°C unless otherwise noted
Max. RF Input Limit must be further limited if input VSWR > 2.5:1
3
Users should avoid exceeding 80% of 2 or more Limits simultaneously
Notes:
•
Operating conditions that exceed the Absolute Maximum Ratings will result in permanent damage to the device.
•
Total Power Dissipation defined as: P
TOT
≡
(P
DC
+ P
IN
) – P
OUT
, where:
P
DC
: DC Bias Power
P
IN
: RF Input Power
P
OUT
: RF Output Power
•
Total Power Dissipation to be de-rated as follows above 22°C:
P
TOT
= 2.2W – (0.0167W/°C) x T
PACK
where T
PACK
=
source lead temperature above 22
°
C
(coefficient of de-rating formula is the Thermal Conductivity)
Example: For a 65°C source lead temperature: P
TOT
= 2.2W – (0.0167 x (65 – 22)) = 1.48W
•
The use of a filled via-hole directly beneath the exposed heatsink tab on the bottom of the package is strongly
recommended to provide for adequate thermal management. Ideally the bottom of the circuit board is
affixed to a heatsink or thermal radiator.
•
HANDLING PRECAUTIONS
To avoid damage to the devices care should be exercised during handling. Proper Electrostatic
Discharge (ESD) precautions should be observed at all stages of storage, handling, assembly, and
testing. These devices should be treated as Class 1A per ESD-STM5.1-1998, Human Body Model.
Further information on ESD control measures can be found in MIL-STD-1686 and MIL-HDBK-263.
APPLICATIONS NOTES & DESIGN DATA
Applications Notes are available from your local Filtronic Sales Representative or directly from the
factory. Complete design data, including S-parameters, noise data, and large-signal models are
available on the Filtronic web site. Evaluation Boards available upon request.
•
Phone:
+1 408 850-5790
Fax:
+1 408 850-5766
http://www.filtronic.co.uk/semis
Revised:
11/14/05
Email:
sales@filcsi.com
L
OW
N
OISE
, H
IGH
L
INEARITY
P
ACKAGED
PHEMTT
FPD1500DFN
•
BIASING GUIDELINES
Active bias circuits provide good performance stabilization over variations of operating
temperature, but require a larger number of components compared to self-bias or dual-biased.
Such circuits should include provisions to ensure that Gate bias is applied before Drain bias,
otherwise the pHEMT may be induced to self-oscillate. Contact your Sales Representative for
additional information.
Dual-bias circuits are relatively simple to implement, but will require a regulated negative
voltage supply for depletion-mode devices such as the FPD1500DFN.
For standard Class A operation, a 50% of I
DSS
bias point is recommended. A small amount of
RF gain expansion prior to the onset of compression is normal for this operating point. Note that
pHEMTs, since they are “quasi- E/D mode” devices, exhibit Class AB traits when operated at
50% of I
DSS
. To achieve a larger separation between P
1dB
and IP3, an operating point in the 25%
to 33% of I
DSS
range is suggested. Such Class AB operation will not degrade the IP3
performance.
PACKAGE OUTLINE
(dimensions in mm)
•
All information and specifications subject to change without notice.
Phone:
+1 408 850-5790
Fax:
+1 408 850-5766
http://www.filtronic.co.uk/semis
Revised:
11/14/05
Email:
sales@filcsi.com
L
OW
N
OISE
, H
IGH
L
INEARITY
P
ACKAGED
PHEMTT
•
PCB FOOT PRINT
FPD1500DFN
•
TYPICAL I-V CHARACTERISTICS
DC IV Curves FPD1500SOT89
0.60
0.50
Drain-Source Current (A)
0.40
0.30
0.20
VG=-1.5V
VG-1.25V
VG=-1.00V
VG=-0.75V
VG=-0.5V
VG=-0.25V
VG=0V
0.10
0.00
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Drain-Source Voltage (V)
Phone:
+1 408 850-5790
Fax:
+1 408 850-5766
http://www.filtronic.co.uk/semis
Revised:
11/14/05
Email:
sales@filcsi.com
L
OW
N
OISE
, H
IGH
L
INEARITY
P
ACKAGED
PHEMTT
FPD1500DFN
Note: The recommended method for measuring I
DSS
, or any particular I
DS
, is to set the Drain-Source
voltage (V
DS
) at 1.3V. This measurement point avoids the onset of spurious self-oscillation which
would normally distort the current measurement (this effect has been filtered from the I-V curves
presented above). Setting the V
DS
> 1.3V will generally cause errors in the current measurements,
even in stabilized circuits.
Recommendation: Traditionally a device’s I
DSS
rating (I
DS
at V
GS
= 0V) was used as a predictor of
RF power, and for MESFETs there is a correlation between I
DSS
and P
1dB
(power at 1dB gain
compression). For pHEMTs it can be shown that there is
no
meaningful statistical correlation
between I
DSS
and P
1dB
; specifically a linear regression analysis shows r
2
< 0.7, and the regression
fails the F-statistic test. I
DSS
is sometimes useful as a guide to circuit tuning, since the S
22
does vary
with the quiescent operating point I
DS
.
Phone:
+1 408 850-5790
Fax:
+1 408 850-5766
http://www.filtronic.co.uk/semis
Revised:
11/14/05
Email:
sales@filcsi.com
